The present invention relates generally to a buffer circuit for a voltage controlled oscillator (VCO), and, more particularly, to a buffer circuit of a VCO used in delayed lock loop and phase locked loop circuitry.
A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates an oscillating signal whose frequency is controlled by an input control voltage. Buffer circuits are commonly used in PLLs to level-shift the oscillating signal. The PLL receives and operates at a supply voltage and the VCO operates at a first voltage level that is less than the supply voltage. The VCO includes a voltage-to-current converter, a current-controlled oscillator (CCO), and a VCO buffer. The voltage-to-current converter converts the input control voltage into a current input and the CCO generates the oscillating signal based on the current input. A ring oscillator is the most commonly used CCO and includes an odd number of cascade-connected inverters that generate oscillating signals that have a known phase difference. Each oscillating signal oscillates from zero to the first voltage level. The buffer circuit is connected to the output of the VCO to level-shift the voltage level of the oscillating signal to the supply voltage in order to obtain a rail-to-rail output voltage.
FIG. 1 shows a conventional VCO buffer circuit 102. The buffer circuit 102 includes first through fourth transistors 104-110. The first transistor 104 has a source connected to a supply voltage and a drain connected to its gate. The second transistor 106 has a source connected to the supply voltage and a gate connected to the gate of the first transistor 104 for receiving a first intermediate signal (VINT_1). The third transistor 108 has a drain connected to the drain of the first transistor 104 for generating the first intermediate signal, a gate for receiving a first input signal (VIN_1), and a source connected to ground. The fourth transistor 110 has a drain connected to the drain of the second transistor 106 for generating an output signal (VOUT), a gate for receiving a second input signal (VIN_2), and a source connected to ground. The first and second transistors 104 and 106 are p-channel metal oxide semiconductor (PMOS) transistors and the third and fourth transistors 108 and 110 are n-channel metal oxide semiconductor (NMOS) transistors. The second input signal is an inverted version of the first input signal.
The first transistor 104 functions as a diode. The first and second transistors 104 and 106 form a current mirror circuit, with the second transistor 106 mirroring a current carried by the first transistor 104. When the first input signal is high, the second input signal is low. The fourth transistor 110 receives the second input signal at logic low state at its gate, and hence is switched OFF. The third transistor 108 receives the first input signal at logic high state at its gate, and hence is switched ON. The third transistor 108 generates the first intermediate signal at logic low state at its drain terminal. The second transistor 106 receives the first intermediate signal at logic low state at its gate and hence is switched ON. The second transistor 106 then generates the output signal at logic high state, thereby buffering the first input signal.
When the first input signal is low, the second input signal is high. The third transistor 108 receives the low first input signal at its gate and hence is switched OFF. The fourth transistor 110 receives the second input signal at logic high state at its gate and hence is switched ON. The fourth transistor 110 generates the output signal at logic low state, thereby buffering the first input signal. However, when the first input signal is high, the first and third transistors 104 and 108 are switched ON. Hence, there is a path from a voltage source (which provides the supply voltage to the buffer circuit 102) to ground through the first and third transistors 104 and 108. This leads to static power dissipation. Therefore, the buffer circuit 102 consumes a large amount of power.
Other conventional techniques for buffering input signals use multiple transistors that function as diodes, and hence, consume a large amount of power. Therefore, it would be advantageous to have a buffer circuit for a VCO that reduces power consumption.